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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad5200/ad5201 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: ? analog devices, inc., functional block diagram ser reg pwr-on preset a w b rdac reg dx 8/6 cs clk sdi ad5200/ad5201 v ss v dd gnd shdn 256-position and 33-position digital potentiometers features ad5200256-position ad520133-position 10 k , 50 k 3-wire spi-compatible serial data input single supply 2.7 v to 5.5 v or dual supply 2.7 v for ac or bipolar operations internal power-on midscale preset applications mechanical potentiometer replacement instrumentation: gain, offset adjustment programmable voltage-to-current conversion programmable filters, delays, time constants line impedance matching general description the ad5200 and ad5201 are programmable resistor devices, with 256 positions and 33 positions respectively, that can be digi- tally controlled through a 3-wire spi serial interface. the terms programmable resistor, variable resistor (vr), and rdac are commonly used interchangeably to refer to digital potentiometers. these devices perform the same electronic adjustment function as a potentiometer or variable resistor. both ad5200/ad5201 contain a single variable resistor in the compact package. each device contains a fixed wiper resistance at the wiper contact that taps the programmable resistance at a point determined by a digital code. the code is loaded in the serial input register. the resistance between the wiper and either end point of the programmable resistor varies linearly with respect to the digital code transferred into the vr latch. each variable resistor offers a completely programmable value of resistance, between the a terminal and the wiper, or the b terminal and the wiper. the fixed a-to-b terminal resistance of 10 k ? or 50 k ? has a nominal temperature coefficient of 500 ppm/ c. the vr has a vr latch that holds its programmed resistance value. the vr latch is updated from an spi-compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. eight data bits for the ad5200 and six data bits for the ad5201 make up the data word that is clocked into the serial input register. the internal preset forces the wiper to the midscale position by loading 80 h and 10 h into ad5200 and ad5201 vr latches respectively. the shdn pin forces the resistor to an end-to-end open-circuit condition on the a terminal and shorts the wiper to the b terminal, achieving a microwatt power shutdown state. when shdn is returned to logic high, the previous latch setting puts the wiper in the same resistance setting prior to shutdown. the digital interface is still active dur- ing shutdown so that code changes can be made that will produce a new wiper position when the device is returned from shutdown. all parts are guaranteed to operate over the extended industrial temperature range of ?0 c to +85 c. 2012 781/461-3113 msop rev. d
C2C ad5200/ad5201?pecifications ad5200 electrical characteristics parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ? 0.25 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ? 0.5 +2 lsb nominal resistor tolerance 3 ? r ab t a = 25 c ?0 +30 % resistance temperature coefficient r ab / ? tv ab = v dd , wiper = no connect 500 ppm/ c wiper resistance r w v dd = 5 v 50 100 ? dc characteristics potentiometer divider mode (specifications apply to all vrs.) resolution n 8 bits differential nonlinearity 4 dnl 1 1/4 +1 lsb integral nonlinearity 4 inl 2 1/2 +2 lsb voltage divider temperature coefficient ? v w / ? t code = 80 h 5 ppm/ c full-scale error v wfse code = ff h ?.5 ?.5 0 lsb zero-scale error v wzse code = 00 h 0 +0.5 +1.5 lsb resistor terminals voltage range 5 v a, b, w v ss v dd v capacitance 6 a, b c a, b f = 1 mhz, measured to gnd, code = 80 h 45 pf capacitance 6 wc w f = 1 mhz, measured to gnd, code = 80 h 60 pf shutdown supply current 7 i dd_sd v dd = 5.5 v 0.01 5 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih 2.4 v input logic low v il 0.8 v input logic high v ih v dd = 3 v, v ss = 0 v 2.1 v input logic low v il v dd = 3 v, v ss = 0 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5p f power supplies logic supply v logic 2.7 5.5 v power single-supply range v dd range v ss = 0 v ?.3 5.5 v power dual-supply range v dd/ss range 2.3 2.7 v positive supply current i dd v ih = +5 v or v il = 0 v 15 40 a negative supply current i ss v ss = ? v 15 40 a power dissipation 8 p diss v ih = +5 v or v il = 0 v, v dd = +5 v, v ss = 0 v 0.2 mw power supply sensitivity pss ? v dd = +5 v 10%, code = midscale ?.01 0.001 +0.01 %/% dynamic characteristics 6, 9 bandwidth ? db bw_10 k ? r ab = 10 k ? , code = 80 h 600 khz bw_50 k ? r ab = 50 k ? , code = 80 h 100 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k ? 0.003 % v w settling time (10 k ? /50 k ? )t s v a = 5 v, v b = 0 v, 1 lsb error band 2/9 s resistor noise voltage density e n_wb r wb = 5 k ? , rs = 0 9 nv hz notes 1 typicals represent average readings at 25 c and v dd = 5 v, v ss = 0 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. i w = v dd /r for both v dd = +2.7 v, v ss = ?.7 v. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. a terminal is open-circuited in shutdown mode. 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v, v ss = 0 v. specifications subject to change without notice. (v dd = 5 v 10%, or 3 v 10%, v ss = 0 v, v a = +v dd , v b = 0 v, ?0 c < t a < +85 c unless otherwise noted.) rev. d
C3C ad5200/ad5201 (v dd = 5 v 10%, or 3 v 10%, v ss = 0 v, v a = +v dd , v b = 0 v, ?0 c < t a < +85 c unless otherwise noted.) ad5201 electrical characteristics parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?.5 0.05 +0.5 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ? 0.1 +1 lsb nominal resistor tolerance 3 ? r ab t a = 25 c ?0 +30 % resistance temperature coefficient r ab / ? tv ab = v dd , wiper = no connect 500 ppm/ c wiper resistance r w v dd = 5 v 50 100 ? dc characteristics potentiometer divider mode (specifications apply to all vrs.) resolution 4 n 6 bits differential nonlinearity 5 dnl ?.5 0.01 +0.5 lsb integral nonlinearity 5 inl 1 0.02 +1 lsb voltage divider temperature coefficient ? v w / ? t code = 10 h 5 ppm/ c full-scale error v wfse code = 20 h ?/2 ?/4 0 lsb zero-scale error v wzse code = 00 h 0 +1/4 +1/2 lsb resistor terminals voltage range 6 v a, b, w v ss v dd v capacitance 7 a, b c a, b f = 1 mhz, measured to gnd, code = 10 h 45 pf capacitance 7 wc w f = 1 mhz, measured to gnd, code = 10 h 60 pf shutdown supply current 8 i dd_sd v dd = 5.5 v 0.01 5 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih 2.4 v input logic low v il 0.8 v input logic high v ih v dd = 3 v, v ss = 0 v 2.1 v input logic low v il v dd = 3 v, v ss = 0 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 7 c il 5p f power supplies logic supply v logic 2.7 5.5 v power single-supply range v dd range v ss = 0 v ?.3 5.5 v power dual-supply range v dd/ss range 2.3 2.7 v positive supply current i dd v ih = +5 v or v il = 0 v 15 40 a negative supply current i ss v ss = ? v 15 40 a power dissipation 9 p diss v ih = +5 v or v il = 0 v, v dd = +5 v, v ss = ? v 0.2 mw power supply sensitivity pss ? v dd = +5 v 10% ?.01 0.001 +0.01 %/% dynamic characteristics 7, 10 bandwidth ? db bw_10 k ? r ab = 10 k ? , code = 10 h 600 khz bw_50 k ? r ab = 50 k ? , code = 10 h 100 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k ? 0.003 % v w settling time (10 k ? /50 k ? )t s v a = 5 v, v b = 0 v, 1 lsb error band 2/9 s resistor noise voltage density e n_wb r wb = 5 k ? , rs = 0 9 nv hz notes 1 typicals represent average readings at 25 c and v dd = 5 v, v ss = 0 v. 2 resistor position nonlinearity error r-inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. r-dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. i w = v dd /r for both v dd = +2.7 v, v ss = ?.7 v. 3 v ab = v dd , wiper (v w ) = no connect. 4 six bits are needed for 33 positions even though it is not a 64-position device. 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 resistor terminals a, b, w have no limitations on polarity with respect to each other. 7 guaranteed by design and not subject to production test. 8 measured at the a terminal. a terminal is open-circuited in shutdown mode. 9 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v, v ss = 0 v. specifications subject to change without notice. rev. d
C4C ad5200/ad5201?pecifications electrical characteristics parameter symbol conditions min typ 1 max unit interface timing characteristics (applies to all parts [notes 2, 3]) input clock pulsewidth t ch , t cl clock level high or low 20 ns data setup time t ds 5n s data hold time t dh 5n s cs setup time t css 15 ns cs high pulsewidth t csw 40 ns clk fall to cs fall hold time t csh0 0n s clk fall to cs rise hold time t csh1 0n s cs rise to clock rise setup t cs1 10 ns notes 1 typicals represent average readings at 25 c and v dd = 5 v, v ss = 0 v. 2 guaranteed by design and not subject to production test. 3 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 2 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switching characteristics are measured using v logic = 5 v. specifications subject to change without notice. (v dd = 5 v 10%, or 3 v 10%, v ss = 0 v, v a = +v dd , v b = 0 v, ?0 c < t a < +85 c unless otherwise noted.) d7 d6 d5 d4 d3 d2 d1 d0 0 1 sdi 0 1 clk 0 1 vout 0 1 cs dac register load figure 1a. ad5200 timing diagram 0 1 sdi d5d4d3d2d1d0 0 1 clk 0 1 cs dac register load 0 1 vout figure 1b. ad5201 timing diagram dx dx 0 1 0 1 0 1 0 v dd sdi (data in) clk cs vout t ch t ds t dh t cs1 t csw t s t cl t csh0 t css 1lsb t csh1 figure 1c. detail timing diagram
ad5200/ad5201 C5C absolute maximum ratings 1 (t a = 25 c, unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3, +7 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, 7 v v a , v b , v w to gnd . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd i max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma 2 digital inputs and output voltage to gnd . . . . . . . 0 v, 7 v operating temperature range . . . . . . . . . . . 40 c to +85 c maximum junction temperature (t j max) . . . . . . . . . 150 c storage temperature . . . . . . . . . . . . . . . . . . 65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . 300 c thermal resistance ja, . . . . . . . . . . . . . 200 c/w package power dissipation = (t j max t a )/ ja notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 max current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. please refer to tpc 31 and tpc 32 for detail. pin configuration top view (not to scale) 10 9 8 7 6 1 2 3 4 5 ad5200/ ad5201 b v ss gnd cs sdi a w v dd shdn clk caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5200/ad5201 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin function descriptions pin name description 1 b b terminal. 2v ss negative power supply, specified for opera- tion from 0 v to 2.7 v. 3 gnd ground. 4 cs chip select input, active low. when cs returns high, data will be loaded into the dac register. 5 sdi serial data input. 6 clk serial clock input, positive edge triggered. 7 shdn active low input. terminal a open circuit. shutdown controls variable resistors of rdac to temporary infinite. 8v dd positive power supply (sum of v dd + v ss 5.5 v). 9 w wiper terminal. 10 a a terminal. msop rev. d
C6C ad5200/ad5201 typical performance characteristics code ?decimal 0.20 rdnl ?lsb 224 0.15 0.10 0.05 0.00 0.05 0.10 0.15 0.20 192 160 128 9664320 256 v dd = 2.7v, v ss = 0v v dd = 5.5v, v ss = 0v v dd = +2.7v, v ss = ?.7v tpc 1. ad5200 10 k ? rdnl vs. code code decimal rdnl lsb 28 0.02 0.01 0.00 0.01 0.02 0.03 24201612 84 032 0.03 v dd = 2.7v, v ss = 0v v dd = 5.5v, v ss = 0v v dd = +2.7v, v ss = 2.7v tpc 2. ad5201 10 k ? rdnl vs. code code decimal rinl lsb 224 0.0 0.1 0.2 0.3 0.5 0.7 192 160 1289664320 256 0.1 v dd = 2.7v, v ss = 0v v dd = 5.5v, v ss = 0v v dd = +2.7v, v ss = 2.7v 0.6 0.4 tpc 3. ad5200 10 k ? rinl vs. code code decimal rinl lsb 28 0.00 0.02 0.04 0.06 0.08 0.12 24201612 84 032 0.02 v dd = +2.7v v ss = 2.7v v dd = 2.7v, v ss = 0v v dd = 5.5v, v ss = 0v 0.10 tpc 4. ad5201 10 k ? rinl vs. code code decimal dnl lsb 224 0.25 0.20 0.15 0.10 0.05 0.10 192 160 1289664320 256 0.30 v dd = +2.7v, v ss = 2.7v v dd = 5.5v, v ss = 0v v dd = 2.7v, v ss = 0v 0.00 0.05 tpc 5. ad5200 10 k ? dnl vs. code code decimal dnl lsb 28 0.005 0.000 0.005 0.010 0.020 24201612 84 03 2 0.010 v dd = +2.7v, v ss = 2.7v v dd = 5.5v, v ss = 0v v dd = 2.7v, v ss = 0v 0.015 tpc 6. ad5201 10 k ? dnl vs. code rev. d
ad5200/ad5201 C7C code decimal inl lsb 224 0.2 0.1 0.0 0.1 0.3 192 160 1289664320 256 0.3 v dd = +2.7v, v ss = 2.7v v dd = 5.5v, v ss = 0v v dd = 2.7v, v ss = 0v 0.2 0.4 0.5 tpc 7. ad5200 10 k ? inl vs. code code decimal inl lsb 28 0.005 0.010 0.020 24201612 84 03 2 0.000 v dd = +2.7v, v ss = 2.7v v dd = 5.5v, v ss = 0v v dd = 2.7v, v ss = 0v 0.015 0.005 0.010 tpc 8. ad5201 10 k ? inl vs. code v ih v i dd /i ss ma 0.01 0.1 10 5.0 4.0 3.0 2.0 1.0 0.0 0.001 1.0 i dd @ v dd /v ss = 5v/0v i dd @ v dd /v ss = 3v/0v i dd @ v dd /v ss = 2.5v i ss @ v dd /v ss = 2.5v tpc 9. supply current vs. logic input voltage temperature c i dd supply current a 20 40 18 16 14 12 10 8 6 4 2 0 20 0 20 40 60 80 100 v il = v ss v ih = v dd v dd = 5.5v v dd = 2.7v tpc 10. supply current vs. temperature temperature c i a shutdown current na 14 40 12 10 8 6 4 2 0 2 20 0 20 40 60 80 100 v dd = 5.5v tpc 11. shutdown current vs. temperature v supply v r on 160 06 140 120 100 80 60 40 20 0 5 4 3 2 1 v dd = 2.7v v dd = 5.5v see test circuit 13 t a = 25 c tpc 12. wiper on resistance vs. v supply rev. d
ad5200/ad5201 C8C fre q uency hz i dd /i ss a 500 10k 450 400 350 300 250 200 150 100 50 0 100k 1m 10m code ff h i ss @ v dd /v ss = 2.5v i dd @ v dd /v ss = 2.5v i dd @ v dd /v ss = 5v/0v i dd @ v dd /v ss = 3v/0v tpc 13. ad5200 10 k ? supply current vs. clock frequency frequency hz i dd /i ss a 500 10k 450 400 350 300 250 200 150 100 50 0 100k 1m 10m code 55 h i ss @ v dd /v ss = 2.5v i dd @ v dd /v ss = 2.5v i dd @ v dd /v ss = 5v/0v i dd @ v dd /v ss = 3v/0v tpc 14. ad5200 10 k ? supply current vs. clock frequency frequency hz psrr db 100 1k 10k 1m +psrr @ v dd = 5v dc 10% p-p ac 100k +psrr @ v dd = 3v dc 10% p-p ac psrr @ v dd = 3v dc 10% p-p ac code = 80 h , v a = v dd , v b = 0v 80 60 40 20 0 tpc 15. power supply rejection ratio vs. frequency frequency hz 6 54 gain db 1k 10k 100k 1m 48 42 36 30 24 18 12 6 0 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h tpc 16. ad5200 10 k ? gain vs. frequency vs. code frequency hz 6 54 gain db 1k 10k 100k 1m 48 42 36 30 24 18 12 6 0 80 h 40 h 20 h 10 h 08 h 04 h 02 h 01 h tpc 17. ad5200 50 k ? gain vs. frequency vs. code frequency hz 6 54 gain db 1k 10k 100k 1m 48 42 36 30 24 18 12 6 0 10 h 8 h 4 h 2 h 1 h tpc 18. ad5201 10 k ? gain vs. frequency vs. code
ad5200/ad5201 C9C frequency hz 6 54 gain db 1k 10k 100k 1m 48 42 36 30 24 18 12 6 0 10 h 8 h 4 h 2 h 1 h tpc 19. ad5201 50 k ? gain vs. frequency vs. code frequency hz 12 48 gain db 1k 10k 100k 1m 42 36 30 24 18 12 6 0 6 10k v in = 100mv rms v dd = 5v r l = 1m 50k tpc 20. ad5200 C3 db bandwidth frequency hz 12 48 gain db 1k 10k 100k 1m 42 36 30 24 18 12 6 0 6 10k v in = 100mv rms v dd = 5v r l = 1m 50k tpc 21. ad5201 C3 db bandwidth frequency hz 12 48 normalized gain flatness 0.1db/div 10 10k 100k 1m 42 36 30 24 18 12 6 0 6 100 1k 50k 10k see test circuit 10 code = 80 h v dd = 5v t a = 25c tpc 22. normalized gain flatness vs. frequency frequency hz 12 48 normalized gain flatness 0.1db/div 10 10k 100k 1m 42 36 30 24 18 12 6 0 6 100 1k 50k 10k see test circuit 10 code = 10 h v dd = 5v t a = 25c tpc 23. ad5201 normalized gain flatness vs. frequency v w (20mv/div) cs (5v/div) tpc 24. one position step change at half scale
ad5200/ad5201 C10C output (2v/div) input (5v/div) tpc 25. large signal settling time v out (20mv/div) tpc 26. digital feedthrough vs. time code decimal 4000 500 potentiometer mode tempco ppm/c 0 3500 3000 2500 2000 1500 1000 500 0 32 64 96 128 160 192 224 256 tpc 27. ad5200 ? v wb / ? t potentiometer mode temperature coefficient code decimal 500 rheostat mode tempco ppm/c 0 3500 3000 2500 2000 1500 1000 500 0 32 64 96 128 160 192 224 256 tpc 28. ad5200 ? r wb / ? t rheostat mode temperature coefficient code decimal potentiometer mode tempco ppm/c 3000 0 2500 2000 1500 1000 500 0 500 4 8 12 16 20 24 28 32 tpc 29. ad5201 potentiometer mode temperature coefficient code decimal potentiometer mode tempco ppm/c 50 0 40 30 20 10 0 20 4 8 12 16 20 24 28 32 1 0 tpc 30. ad5201 ? v wb / ? t potentiometer mode tempco
ad5200/ad5201 C11C code decimal 100.0 10.0 0.1 032 theoretical i max ma 1.0 64 96 128 160 192 224 256 r ab = 10k r ab = 50k tpc 31. ad5200 i max vs. code code decimal 100.0 10.0 0.1 04 theoretical i max ma 1.0 812 16 20 24 28 32 r ab = 10k r ab = 50k tpc 32. ad5201 i max vs. code operation the ad5200/ad5201 provide 255 and 33 positions digitally- controlled variable resistor (vr) devices. changing the programmed vr settings is accomplished by clocking in an 8-bit serial data word for ad5200, and a 6-bit serial data word for ad5201, into the sdi (serial data input) pins. table i pro vides the serial register data word format. the ad5200/ad5201 are preset to a midscale internally during power-on condition. in addition, the ad5200/ad5201 contain power shutdown shdn pins that place the rdac in a zero power consump- tion state where the immediate switches next to terminals a and b are open-circuited. meanwhile, the wiper w is connected to b terminal, resulting in only leakage current consumption in the vr structure. during shutdown, the vr latch contents are maintained when the rdac is inactive. when the part is returned from shutdown, the stored vr setting will be applied to the rdac. table i. ad5200 serial-data word format 7 b6b5b4b3b2b1b0 b 7 d6d5d4d3d2d1d0 d bs mb sl 2 7 2 0 table ii. ad5201 serial-data word format 5b * 4 b3 b2 b1 b0 b 5d * 4 d3 d2 d1 d0 d bs mb sl 2 5 2 0 * six data bits are needed for 33 positions. programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a and b are available with values of 10 k ? and 50 k ? . the final two digits of the part number determine the nominal resistance value, e.g., 10 k ? = 10 and 50 k ? = 50. the nominal resistance (r ab ) of ad5200 has 256 contact points accessed by the wiper terminal. the 8-bit data word in the rdac latch of ad5200 is decoded to select one of the 256 possible settings. in both parts, the wiper s first connection starts at the b terminal for data 00 h . this b-terminal connection has a wiper contact resistance of 50 ? as long as valid v dd /v ss is applied, regardless of the nominal resistance. for a 10 k ? part, the second connection of ad5200 is the first tap point with 89 ? [r wb = r ab /255 + r w = 39 ? + 50 ? ] for data 01 h . the third connection is the next tap point representing 78 + 50 = 128 ? for data 02 h . due to its unique internal struc ture, ad5201 has 5-bit + 1 resolution, but needs a 6-bit data word to achieve the full 33 steps resolution. the 6-bit data word in the rdac latch is decoded to select one of the 33 possible settings. data 34 to 63 will automatically be equal to position 33. the wiper 00 h connection of ad5201 gives 50 ? . similarly, for a 10 k ? part, the first tap point of ad5201 yields 363 ? for data 01 h , 675 ? for data 02 h . for both ad5200 and ad5201, each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached. figures 2a and 2b show the simplified diagrams of the equivalent rdac circuits.
ad5200/ad5201 C12C d7 d6 d5 d4 d3 d2 d1 d0 rdac latch & decoder shdn sw shdn sw 2 n 1 sw 2 n 2 sw 1 sw 0 a r r r b w digital circuitry omitted for clarity r r ab 2 n 1 figure 2a. ad5200 equivalent rdac circuit. 255 positions can be achieved up to switch sw 2 n C1 . sw 2 n 1 d5 d4 d3 d2 d1 d0 rdac latch & decoder sw 2 n 2 sw 1 sw 0 r r r r b w digital circuitry omitted for clarity shdn a sw shdn sw 2 n r r ab 2 n figure 2b. ad5201 equivalent rdac circuit. unlike ad5200, 33 positions can be achieved all the way to switch sw 2 n . the general equation determining the digitally programmed output resistance between w and b is: rd d r wb ab () =+ 255 50 ? for ad5200 (1) rd d r wb ab () =+ 32 50 ? for ad5201 (2) where: d is the decimal equivalent of the data contained in rdac latch. r ab is the nominal end-to-end resistance. r w is the wiper resistance contributed by the on-resistance of the internal switch. note d in ad5200 is between 0 to 255 for 256 positions. on the other hand, d in ad5201 is between 0 to 32 so that 33 positions can be achieved due to the slight internal structure difference, figure 2b. again if r ab = 10 k ? and a terminal can be opened or tied to w, the following output resistance between w to b will be set for the following rdac latch codes: ad5200 wiper-to-b resistance dr wb (dec) ( ) output state 255 10050 full-scale (r ab + r w ) 128 5070 midscale 189 1 lsb 0 50 zero-scale (wiper contact resistance) ad5201 wiper-to-b resistance dr wb (dec) ( ) output state 32 10050 full-scale (r ab + r w ) 16 5050 midscale 1 363 1 lsb 0 50 zero-scale (wiper contact resistance) note that in the zero-scale condition a finite wiper resistance of 50 ? is present. care should be taken to limit the current flow between w and b in this state to no more than 20 ma to avoid degradation or possible destruction of the internal switch contact. like the mechanical potentiometer the rdac replaces, it is totally symmetrical. the resistance between the wiper w and terminal a also produces a digitally controlled resistance r wa . when these terminals are used, the b terminal should be tied to the wiper. setting the resistance value for r wa starts at a maxi- mum value of resistance and decreases as the data loaded in the latch is increased in value. the general equation for this operation is: rd d r wa ab () = ? () + 255 255 50 ? for ad5200 (3) rd d r wa ab () = ? () + 32 32 50 ? for ad5201 (4) similarly, d in ad5200 is between 0 to 255, whereas d in ad5201 is between 0 to 32. for r ab = 10 k ? and b terminal is opened or tied to the wiper w, the following output resistance between w and a will be set for the following rdac latch codes:
ad5200/ad5201 C13C ad5200 wiper-to-a resistance dr wa (dec) ( ) output state 255 50 full-scale (r w ) 128 5030 midscale 1 10011 1 lsb 0 10050 zero-scale (r ab + r w ) ad5201 wiper-to-a resistance dr wa (dec) ( ) output state 32 50 full-scale (r w ) 16 5050 midscale 1 9738 1 lsb 0 10050 zero-scale (r ab + r w ) the tolerance of the nominal resistance can be 30% due to process lot dependance. if users apply the rdac in rheostat (variable resistance) mode, they should be aware of such specifi- cation of tolerance. the change in r ab with temperature has a 500 ppm/ c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer easily generates output voltages at wiper-to-b and wiper-to-a to be proportional to the input volt- age at a to b. unlike the polarity of v dd v ss , which must be positive, volt- age across a b, w a, and w b can be at either polarity. if ignoring the effects of the wiper resistance for an approxima- tion, connecting a terminal to 5 v and b terminal to ground produces an output voltage at the wiper which can be any value starting at almost zero to almost full scale with the minor devia- tion contributed by the wiper resistance. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 2 n -1 and 2 n position resolution of the potentiometer divider for ad5200 and ad5201 respectively. the general equation defin- ing the output voltage with respect to ground for any valid input voltage applied to terminals a and b is: vd d vv wa b b () =+ 255 for ad5200 (5) vd d vv wa bb () =+ 32 for ad5201 (6) where d in ad5200 is between 0 to 255 and d in ad5201 is between 0 to 32. for more accurate calculation, including the effects of wiper resistance, v w can be found as: vd rd r v rd r v w wb ab a wa ab b () = () + () (7) where r wb ( d ) and r wa ( d ) can be obtained from equations 1 to 4. operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. here the output voltage is dependent on the ratio of the internal resistors and not the absolute values; therefore, the drift reduces to 15 ppm/ c. digital interfacing the ad5200/ad5201 contain a standard three-wire serial input control interface. the three inputs are clock (clk), cs, and serial data input (sdi). the positive-edge-sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. if mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. figure 3 shows more detail of the internal digital circuitry. when cs is low, the clock loads data into the serial register on each positive clock edge (see table iii). ser reg pwr-on preset v ss a w b shdn rdac reg dx 8/6 v dd cs clk sdi gnd ad5200/ad5201 figure 3. block diagram table iii. input logic control truth table clk cs shdn register activity l l h no sr effect. p l h shift one bit in from the sdi pin. x p h load sr data into rdac latch. x h h no operation. x h l open circuit on a terminal and short circuit between w to b terminals. note p = positive edge, x = don t care, sr = shift register. all digital inputs are protected with a series input resistor and parallel zener esd structure shown in figure 4. applies to digital input pins cs , sdi, shdn , clk. 340 logic v ss figure 4. esd protection of digital pins a,b,w v ss figure 5. esd protection of resistor terminals
ad5200/ad5201 C14C test circuits figures 6 to 14 define the test conditions used in the product specification table. v ms a w b dut v+ v+ = v dd 1 lsb = v+/2 n figure 6. potentiometer divider nonlinearity error test circuit (inl, dnl) v ms a w b dut no connect i w figure 7. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) v ms1 a w b dut i w = v dd /r nominal v ms2 v w r w = [v ms1 v ms2 ]/i w figure 8. wiper resistance test circuit v ms % v dd % pss (%/%) = v+ = v dd 10% psrr (db) = 20 log v ms v dd v ms a w b v+ v dd v a figure 9. power supply sensitivity test circuit (pss, psrr) op279 w 5v b v out offset gnd offset bias a dut v in figure 10. inverting gain test circuit offset bias b offset gnd a dut op279 w 5v v out v in figure 11. noninverting gain test circuit op42 v out v in +15v offset gnd 15v w b a 2.5v figure 12. gain vs. frequency test circuit w b v ss to v dd dut i sw code = oo h r sw = 0.1v i sw 0.1v + figure 13. incremental on resistance test circuit i cm a w b nc gnd nc v ss v dd dut v cm nc = no connect figure 14. common-mode leakage current test circuit
ad5200/ad5201 rev. d C15C outline dimensions figure 15. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 res k temperature range package description package option full reel qty. branding information ad5200brmz10 256 10 ?40c to +85c 10-lead msop rm-10 50 dla ad5200brmz10-reel7 256 10 ?40c to +85c 10-lead msop rm-10 1,000 dla ad5200brmz50 256 50 ?40c to +85c 10-lead msop rm-10 50 d8 t ad5200brmz50-reel7 256 50 ?40c to +85c 10-lead msop rm-10 1,000 d8 t ad5201brmz10 33 10 ?40c to +85c 10-lead msop rm-10 50 dma ad5201brmz10-reel7 33 10 ?40c to +85c 10-lead msop rm-10 1,000 dma ad5201brmz50 33 50 ?40c to +85c 10-lead msop rm-10 50 dmb ad5201brmz50-reel7 33 50 ?40c to +85c 10-lead msop rm-10 1,000 dmb 1 z = rohs compliant part. revision history 12/12rev. c to rev. d changes to ordering guide ........................................................... 15 6/12rev. b to rev. c removed digital potentiometer selection guide ....................... 15 updated outline dimensions ........................................................ 15 changes to ordering guide ........................................................... 15 8/01rev. a to rev. b edits to ordering guide .......................................................... 5 2/01rev. 0 to rev. a edits to ordering guide .......................................................... 5 edits to absolute maximum ratings ............................... 5 tpcs 31 and 32 added .................................................................... 11 compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02188-0-12/12(d)

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